The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2015

Filed:

Mar. 30, 2012
Applicants:

Daewon Yang, Hopewell Junction, NY (US);

Kangguo Cheng, Hopewell Junction, NY (US);

Pavel Smetana, Hopewell Junction, NY (US);

Richard S. Wise, Hopewell Junction, NY (US);

Keith Kwong Hon Wong, Hopewell Junction, NY (US);

Inventors:

Daewon Yang, Hopewell Junction, NY (US);

Kangguo Cheng, Hopewell Junction, NY (US);

Pavel Smetana, Hopewell Junction, NY (US);

Richard S. Wise, Hopewell Junction, NY (US);

Keith Kwong Hon Wong, Hopewell Junction, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
C23C 16/507 (2006.01); C23C 16/34 (2006.01); C23C 16/40 (2006.01); C23C 16/455 (2006.01); C23C 16/458 (2006.01); C23C 16/56 (2006.01); H01J 37/20 (2006.01); H01J 37/32 (2006.01); H01L 27/108 (2006.01); H01L 21/316 (2006.01); H01L 21/318 (2006.01);
U.S. Cl.
CPC ...
C23C 16/507 (2013.01); C23C 16/345 (2013.01); C23C 16/402 (2013.01); C23C 16/4586 (2013.01); C23C 16/45578 (2013.01); C23C 16/56 (2013.01); H01J 37/20 (2013.01); H01J 37/321 (2013.01); H01L 27/10867 (2013.01); H01J 2237/20207 (2013.01); H01J 2237/3323 (2013.01); H01L 21/3185 (2013.01); H01L 21/31608 (2013.01);
Abstract

Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.


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