The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Mar. 15, 2013
Applicants:

Yaojian Lin, Singapore, SG;

IL Kwon Shim, Singapore, SG;

Junmo Koo, Singapore, SG;

Jose Alvin Caparas, Singapore, SG;

Inventors:

Yaojian Lin, Singapore, SG;

Il Kwon Shim, Singapore, SG;

JunMo Koo, Singapore, SG;

Jose Alvin Caparas, Singapore, SG;

Assignee:

STATS ChipPAC Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/16 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49811 (2013.01); H01L 21/76885 (2013.01); H01L 24/19 (2013.01); H01L 23/16 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/73267 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/3511 (2013.01); H01L 23/49816 (2013.01);
Abstract

An integrated circuit packaging system and method of manufacture thereof includes: a substrate having a top insulation layer and a top conductive layer; an inter-react layer on the substrate; an integrated circuit die on the substrate; a package body on the inter-react layer and the integrated circuit die; and a top solder bump on the top conductive layer, the top solder bump in a 3D via formed through the package body, the inter-react layer, and the top insulation layer for exposing the top conductive layer in the 3D via.


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