The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2015

Filed:

Jun. 25, 2013
Applicant:

Hong Kong Applied Science & Technology Research Institute Company Limited, Hong Kong, HK;

Inventors:

Xiao Huo, Hong Kong, HK;

Beiping Yan, Hong Kong, HK;

Xiaowu Cai, Shenzhen, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01); H02H 9/04 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H02H 9/046 (2013.01); H01L 27/0248 (2013.01); H01L 27/0259 (2013.01);
Abstract

An electro-static-discharge (ESD) protection circuit has a vertical NPN transistor with a floating p-type base created by a deep p-type implant under an N+ source region. The deep p-type implant may be an ESD implant in a standard CMOS process. The p-type implant provides a low initial snap-back trigger voltage, but the holding voltage may be too low, creating latch-up problems. The holding voltage is raised by about one volt by connecting the emitter of the vertical NPN transistor to parallel resistor and diode paths. When the vertical NPN transistor is triggered, its current initially flows through the resistor, creating an increasing voltage drop through the resistor as current rises. Once the voltage across the resistor reaches 0.5 volt, the diode in parallel with the resistor becomes forward biased and shunts a higher current than the resistor, raising the holding voltage. A clamp transistor may replace the diode.


Find Patent Forward Citations

Huo, Xiao. (2015). Electro-static-discharge (esd) protection structure with stacked implant junction transistor and parallel resistor and diode paths to lower trigger voltage and raise holding volatge (U.S. Patent No. 9054521). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9054521

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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