The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2015

Filed:

Nov. 26, 2013
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

An-Chi Liu, Tainan, TW;

Chun-Hsien Lin, Tainan, TW;

Yu-Cheng Tung, Kaohsiung, TW;

Chien-Ting Lin, Hsinchu, TW;

Wen-Tai Chiang, Tainan, TW;

Shih-Hung Tsai, Tainan, TW;

Ssu-I Fu, Kaohsiung, TW;

Ying-Tsung Chen, Kaohsiung, TW;

Chih-Wei Chen, Taichung, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7834 (2013.01); H01L 29/785 (2013.01); H01L 29/78654 (2013.01); H01L 29/66795 (2013.01);
Abstract

A non-planar semiconductor structure comprises a substrate, at least one fin structure on the substrate, a gate covering parts of the fin structures and part of the substrate such that the fin structure is divided into a channel region stacking with the gate and source/drain region at both sides of the gate, a plurality of epitaxial structures covering on the source/drain region of the fin structures, a recess is provided between the channel region of the fin structure and the epitaxial structure, and a spacer formed on the sidewalls of the gate and the epitaxial structures, wherein the portion of the spacer filling in the recesses is flush with the top surface of the epitaxial structures.


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