The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2015

Filed:

Jul. 31, 2013
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Bing Li, Singapore, SG;

Sung Mun Jung, Singapore, SG;

Yi Tat Lim, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66825 (2013.01);
Abstract

Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory gate stack, removing the capping layer from over the memory array region and the high-voltage MOSFET region, forming a second silicon material layer over the capping layer and over the first silicon material layer, and removing the second silicon material layer. The method further includes removing the capping layer from over the first silicon material layer in the logic device region and removing the first and second silicon material layers from the high-voltage MOSFET region. Still further, the method includes forming a photoresist material layer over the memory array region and the logic device region and exposing the semiconductor substrate to an ion implantation process.


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