The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2015

Filed:

Jun. 18, 2013
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Ming-Te Wei, Changhua County, TW;

Po-Chao Tsao, New Taipei, TW;

Ching-Li Yang, Ping-Tung Hsien, TW;

Chien-Yang Chen, Kaohsiung, TW;

Hui-Ling Chen, Kaohsiung, TW;

Guan-Kai Huang, Tainan, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 21/78 (2006.01); H01L 23/58 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/76838 (2013.01); H01L 21/78 (2013.01); H01L 23/585 (2013.01);
Abstract

A die seal ring is provided. The die seal ring includes a substrate and a first layer extruding from the substrate. The first layer has a first fin ring structure and a layout of the first fin ring structure has a stamp-like shape. In addition, a method for forming a die seal ring is provided. A substrate having an active region is provided. A patterned sacrificial layer is formed on the substrate. A spacer is formed on the sidewall of the patterned sacrificial layer. The patterned sacrificial layer is removed. The substrate is patterned by using the spacer as a mask, thereby simultaneously forming at least a fin structure of a Fin-FET and a first layer of the die seal ring.


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