The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2015

Filed:

Jul. 24, 2013
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Sheng-Chau Chen, Kaohsiung, TW;

Chih-Hui Huang, Yongkang, TW;

Yeur-Luen Tu, Taichung, TW;

Cheng-Ta Wu, Shueishang Township, TW;

Chia-Shiung Tsai, Hsin-Chu, TW;

Xiao-Meng Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/30 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 21/18 (2006.01); H01L 21/67 (2006.01); H01L 33/00 (2010.01);
U.S. Cl.
CPC ...
H01L 21/02068 (2013.01); H01L 21/76843 (2013.01); H01L 21/187 (2013.01); H01L 21/67017 (2013.01); H01L 21/02334 (2013.01); H01L 33/0079 (2013.01); H01L 21/02041 (2013.01); H01L 21/02074 (2013.01); Y10S 438/906 (2013.01);
Abstract

Embodiments of mechanisms for cleaning a surface of a semiconductor wafer for a hybrid bonding are provided. The method for cleaning a surface of a semiconductor wafer for a hybrid bonding includes providing a semiconductor wafer, and the semiconductor wafer has a conductive pad embedded in an insulating layer. The method also includes performing a plasma process to a surface of the semiconductor wafer, and metal oxide is formed on a surface of the conductive structure. The method further includes performing a cleaning process using a cleaning solution to perform a reduction reaction with the metal oxide, such that metal-hydrogen bonds are formed on the surface of the conductive structure. The method further includes transferring the semiconductor wafer to a bonding chamber under vacuum for hybrid bonding. Embodiments of mechanisms for a hybrid bonding and a integrated system are also provided.


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