The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2015

Filed:

Nov. 18, 2013
Applicant:

Alpha and Omega Semiconductor Incorporated, Sunnyvale, CA (US);

Inventors:

Jun Lu, San Jose, CA (US);

Kai Liu, Mountain View, CA (US);

Yan Xun Xue, Los Gatos, CA (US);

Assignee:

Alpha & Omega Semiconductor, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 25/07 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/565 (2013.01); H01L 23/49517 (2013.01); H01L 23/49524 (2013.01); H01L 23/49551 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 24/34 (2013.01); H01L 25/07 (2013.01); H01L 23/3107 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01082 (2013.01); H01L 24/48 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01075 (2013.01); H01L 2924/014 (2013.01); H01L 2924/13091 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/40137 (2013.01); H01L 2224/73263 (2013.01); H01L 2224/37011 (2013.01); H01L 2924/1306 (2013.01);
Abstract

A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding.


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