The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2015

Filed:

Jun. 23, 2011
Applicants:

Emmanuel Espiritu, Singapore, SG;

Elizar Andres, Singapore, SG;

Henry Descalzo Bathan, Singapore, SG;

Zigmund Ramirez Camacho, Singapore, SG;

Inventors:

Emmanuel Espiritu, Singapore, SG;

Elizar Andres, Singapore, SG;

Henry Descalzo Bathan, Singapore, SG;

Zigmund Ramirez Camacho, Singapore, SG;

Assignee:

STATS ChipPAC Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49548 (2013.01); H01L 23/49503 (2013.01); H01L 23/49582 (2013.01); H01L 21/4832 (2013.01); H01L 24/48 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/01327 (2013.01); H01L 2224/32257 (2013.01); H01L 23/3107 (2013.01); H01L 24/49 (2013.01); H01L 2224/2919 (2013.01);
Abstract

A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent to the package paddle; depositing a lead conductive cap on the lead, the lead conductive cap includes a nickel layer having a thickness between 2.55 μm to 8.00 μm deposited on the lead, a palladium layer deposited on the nickel layer, and a gold layer deposited on the palladium layer; mounting an integrated circuit over the package paddle; attaching an electrical connector between the lead conductive cap and the integrated circuit; and forming an encapsulation over the integrated circuit, a portion of the lead, and a portion of the package paddle.


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