The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2015

Filed:

Mar. 12, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Yanfeng Wang, Fishkill, NY (US);

Dechao Guo, Fishkill, NY (US);

Darsen Lu, Yorktown Heights, NY (US);

Philip J. Oldiges, Lagrangeville, NY (US);

Gan Wang, Fishkill, NY (US);

Xin Wang, Beacon, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66477 (2013.01); H01L 29/78 (2013.01); H01L 29/785 (2013.01); H01L 29/66772 (2013.01); H01L 21/823481 (2013.01); H01L 21/823878 (2013.01); H01L 29/7848 (2013.01); H01L 29/7842 (2013.01); H01L 29/66795 (2013.01);
Abstract

A finFET and method of fabrication are disclosed. A sacrificial layer is formed on a bulk semiconductor substrate. A top semiconductor layer (such as silicon) is disposed on the sacrificial layer. The bulk semiconductor substrate is recessed in the area adjacent to the transistor gate and a stressor layer is formed in the recessed area. The sacrificial layer is selectively removed and replaced with an insulator, such as a flowable oxide. The insulator provides isolation between the transistor channel and the bulk substrate without the use of dopants.


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