The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2015

Filed:

Jun. 15, 2012
Applicants:

Yu-lin Yen, Taipei, TW;

Chien-hui Chen, Zhongli, TW;

Tsang-yu Liu, Zhubei, TW;

Yen-shih Ho, Kaohsiung, TW;

Inventors:

Yu-Lin Yen, Taipei, TW;

Chien-Hui Chen, Zhongli, TW;

Tsang-Yu Liu, Zhubei, TW;

Yen-Shih Ho, Kaohsiung, TW;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3128 (2013.01); H01L 23/3114 (2013.01); H01L 23/481 (2013.01); H01L 2224/131 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13024 (2013.01); H01L 2924/1461 (2013.01); H01L 2224/0401 (2013.01);
Abstract

An embodiment of the invention provides a chip package which includes: a substrate having a plurality of sides and a plurality of corner regions, wherein each of the corner regions is located at an intersection of at least two of the sides of the substrate; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a carrier substrate, wherein the substrate is disposed on the carrier substrate, and the substrate has a recess extending towards the carrier substrate in at least one of the corner regions.


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