The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2015
Filed:
Aug. 12, 2013
Applicant:
United Microelectronics Corp., Hsinchu, TW;
Inventors:
Chun-Hung Chen, Tainan, TW;
Ming-Tse Lin, Hsinchu, TW;
Chien-Li Kuo, Hsinchu, TW;
Kuei-Sheng Wu, Miaoli County, TW;
Assignee:
United Microelectronics Corp., Hsinchu, TW;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 21/00 (2006.01); H01L 23/60 (2006.01); H01L 49/02 (2006.01); H01L 23/14 (2006.01); H01L 23/498 (2006.01); H01L 23/64 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/60 (2013.01); H01L 28/10 (2013.01); H01L 23/147 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/5225 (2013.01); H01L 23/5227 (2013.01); H01L 23/645 (2013.01);
Abstract
A semiconductor structure is provided. The semiconductor structure includes an interposer structure. The interposer structure includes an interposer substrate, a ground, through vias, a dielectric layer, and an inductor. The through vias are formed in the interposer substrate and electrically connected to the ground. The dielectric layer is on the interposer substrate. The inductor is on the dielectric layer.