The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2015

Filed:

Feb. 05, 2013
Applicant:

Hong Kong Applied Science & Technology Research Institute Company Limited, Hong Kong, HK;

Inventors:

Zhongzi Chen, Hong Kong, HK;

Beiping Yan, Hong Kong, HK;

Xiao Huo, Hong Kong, HK;

Xiaowu Cai, Shenzhen, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/02 (2006.01); G06F 1/03 (2006.01);
U.S. Cl.
CPC ...
G06F 1/0321 (2013.01);
Abstract

A sine wave generator for a Direct Digital Synthesizer (DDS) converts a digital phase input into a digital sine wave output. Sine values and slopes are stored in read-only memory (ROM) for coarse upper phase bits in a first quadrant. A quadrant folder and phase splitter reflects and inverts values from the first quadrant to generate amplitudes for all four quadrants. Each sine value and slope is stored for a range of lower phase bits. A Delta bit separates upper and lower phase bits. Delta conditionally inverts the lower phase bits, the sine value, and the final polarity. A reduced AND logic array multiplies the slope by the conditionally inverted lower phase bits. A reconstructed ADD logic array then adds the conditionally inverted sine value. The conditionally inverted polarity is added to generate the final sine value. Sine generation logic is streamlined with conditional inversion based on the Delta bit.


Find Patent Forward Citations

Chen, Zhongzi. (2015). Phase-to-amplitude converter for direct digital synthesizer (dds) with reduced and and reconstructed add logic arrays (U.S. Patent No. 9021002). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9021002

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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