The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2015

Filed:

Oct. 18, 2012
Applicant:

Stmicroelectronics (Grenoble 2) Sas, Grenoble, FR;

Inventors:

Dominique Marais, La Terrasse, FR;

Jacques Chavade, Moirans, FR;

Rémi Brechignac, Grenoble, FR;

Eric Saugier, Villard Bonnot, FR;

Romain Coffy, Saint Martin le Vinoux, FR;

Luc Petit, Fontaine, FR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 23/367 (2006.01); H01L 25/065 (2006.01); H05K 1/02 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 23/3677 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/00 (2013.01); H01L 2924/00012 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/3011 (2013.01); H05K 1/0206 (2013.01); H05K 3/3436 (2013.01); H05K 2201/10515 (2013.01); H05K 2201/1053 (2013.01);
Abstract

An electronic package includes a substrate wafer with an interconnect network. A first chip is fixed to a front of the substrate, connected to the interconnect network and encapsulated by a body. A second chip is placed on a back side of the substrate wafer and connected to the interconnect network by back-side connection elements interposed between the back side of the substrate and a front side of the second chip. Front-side connection elements are placed on the front side of the substrate and connected to the interconnect network. The connection elements extend beyond the frontal face of the body. The package may be mounted on a board with an interposed thermally conductive material.


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