The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2015

Filed:

Jul. 02, 2014
Applicant:

Siliconware Precision Industries Co., Ltd., Taichung, TW;

Inventors:

Chi-Ching Ho, Taichung, TW;

Yu-Chih Yu, Taichung, TW;

Ying-Chou Tsai, Taichung, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/50 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4825 (2013.01); H01L 21/4828 (2013.01); H01L 21/486 (2013.01); H01L 21/4875 (2013.01); H01L 21/56 (2013.01); H01L 21/561 (2013.01); H01L 23/3128 (2013.01); H01L 23/49827 (2013.01); H01L 23/49861 (2013.01); H01L 24/83 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/00014 (2013.01);
Abstract

A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; forming a first encapsulant in the first openings; forming a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer.


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