The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2015
Filed:
Feb. 03, 2012
Roland Daniel Rosezin, Bernau am Chiemsee, DE;
Florian Lentz, Pulheim, DE;
Rainer Bruchhaus, Munich, DE;
Eike Linn, Wuerselen, DE;
Ilia Valov, Aachen, DE;
Rainer Waser, Aachen, DE;
Stefan Tappertzhofen, Aachen, DE;
Lutz Nielen, Aachen, DE;
Roland Daniel Rosezin, Bernau am Chiemsee, DE;
Florian Lentz, Pulheim, DE;
Rainer Bruchhaus, Munich, DE;
Eike Linn, Wuerselen, DE;
Ilia Valov, Aachen, DE;
Rainer Waser, Aachen, DE;
Stefan Tappertzhofen, Aachen, DE;
Lutz Nielen, Aachen, DE;
Forschungszentrum Juelich GmbH, Juelich, DE;
Rheinisch-Westfaelische Technische Hochschule Aachen (RWTH), Aachen, DE;
Abstract
A method for reading out a memory element comprises a series connection. of at least two memory cells A and B each have a stable state A0 or B0 having higher resistance and a stable state A1 or B1 having lower electrical resistance. An electrical variable of the series circuit is measured and an electrical variable is selected for this measurement, to which the memory cell A in state A0 makes a different contribution than the memory cell B in state B0 and/or to which the memory cell A instate A1 makes a different contribution than the memory cell B in state B1. The two state combinations A1 and B0 or A0 and B1 then result in differing values for the electrical variable that is measured by way of the series circuit. These state combinations can thus be distinguished from each other without having to change the logic state of the memory element during reading.