The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 2015
Filed:
Jul. 18, 2012
Veeraraghavan S. Basker, Schenectady, NY (US);
Kangguo Cheng, Schenectady, NY (US);
Bruce B. Doris, Brewster, NY (US);
Terence B. Hook, Jericho Center, VT (US);
Ali Khakifirooz, Albany, NY (US);
Pranita Kulkarni, Mount Kisco, NY (US);
Tenko Yamashita, Schenectady, NY (US);
Chun-chen Yeh, Clifton Park, NY (US);
Veeraraghavan S. Basker, Schenectady, NY (US);
Kangguo Cheng, Schenectady, NY (US);
Bruce B. Doris, Brewster, NY (US);
Terence B. Hook, Jericho Center, VT (US);
Ali Khakifirooz, Albany, NY (US);
Pranita Kulkarni, Mount Kisco, NY (US);
Tenko Yamashita, Schenectady, NY (US);
Chun-Chen Yeh, Clifton Park, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.