The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2015

Filed:

Sep. 30, 2011
Applicants:

Feng-chi Hung, Chu-Bei, TW;

Jhy-jyi Sze, Hsin-Chu, TW;

Shou-gwo Wuu, Hsin-Chu, TW;

Inventors:

Feng-Chi Hung, Chu-Bei, TW;

Jhy-Jyi Sze, Hsin-Chu, TW;

Shou-Gwo Wuu, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/062 (2012.01); H01L 31/113 (2006.01); H01L 21/265 (2006.01); H01L 29/78 (2006.01); H01L 27/146 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 21/26506 (2013.01); H01L 29/78 (2013.01); H01L 27/14603 (2013.01); H01L 27/14612 (2013.01); H01L 27/1463 (2013.01); H01L 21/28123 (2013.01); H01L 21/2822 (2013.01);
Abstract

Transistors, methods of manufacturing thereof, and image sensor circuits with reduced random telegraph signal (RTS) noise are disclosed. In one embodiment, a transistor includes a channel disposed between two isolation regions in a workpiece. The channel has edge regions proximate the isolation regions and a central region between the edge regions. The transistor includes a gate dielectric disposed over the channel, and a gate disposed over the gate dielectric. The transistor includes a voltage threshold modification feature proximate the edge regions configured to increase a voltage threshold of the transistor proximate edge regions relative to the central region of the channel.


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