The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 2015
Filed:
Nov. 03, 2011
Chia-wen Liu, Taipei, TW;
Tsung-hsing Yu, Taipei, TW;
Dhanyakumar Mahaveer Sathaiya, Hsinchu, TW;
Wei-hao Wu, Hsinchu, TW;
Ken-ichi Goto, Hsin-Chu, TW;
Tzer-min Shen, Hsinchu, TW;
Zhiqiang Wu, Hsinchu, TW;
Chia-Wen Liu, Taipei, TW;
Tsung-Hsing Yu, Taipei, TW;
Dhanyakumar Mahaveer Sathaiya, Hsinchu, TW;
Wei-Hao Wu, Hsinchu, TW;
Ken-Ichi Goto, Hsin-Chu, TW;
Tzer-Min Shen, Hsinchu, TW;
Zhiqiang Wu, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.