The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2015
Filed:
Nov. 09, 2011
Dominic Koey Poh Meng, Kuala Lumpur, MY;
Zhiwei Gong, Chandler, AZ (US);
Kesvakumar V. C. Muniandy, Klang, MY;
Weng Foong Yap, Shah Alam, MY;
Dominic Koey Poh Meng, Kuala Lumpur, MY;
Zhiwei Gong, Chandler, AZ (US);
Kesvakumar V. C. Muniandy, Klang, MY;
Weng Foong Yap, Shah Alam, MY;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a predetermined position on a substrate, panel or tape during processing of semiconductor dies that are embedded into redistributed chip package (RCP) or wafer level package (WFL) panels. The embedded unit provides the functionality and design flexibility to run a number of embedded units and semiconductor dies or components having different sizes and dimensions in a single processing panel or batch and reduces die drift, movement or skew during encapsulation and post-encapsulation cure.