The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2015

Filed:

Aug. 16, 2013
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Chien-Chung Chen, Pingtung County, TW;

Ming-Tung Lee, Taoyun County, TW;

Yin-Fu Huang, Taiwan, TW;

Shih-Chin Lien, Taipei Country, TW;

Shyi-Yuan Wu, Taipei Country, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0847 (2013.01); H01L 21/26513 (2013.01); H01L 29/66772 (2013.01); H01L 29/78654 (2013.01);
Abstract

A semiconductor device having a well, a p well implant bounded at least in part within a substrate by the well, a conductive layer disposed on the substrate, a high voltage n− (HVN−) doped well implanted in the p well implant, a high voltage p doped (HVPD) well implanted in the p well implant, and a drain n− well and a source n− well disposed in the HVN− doped well and HVPD well, respectively, is provided. A method of fabricating the semiconductor device is also provided. In certain embodiments, the method of fabricating the semiconductor device is characterized by implanting the HVN− ions at a first tilt angle and/or implanting the HVPD ions at a second tilt angle.


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