The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2015
Filed:
Apr. 09, 2012
Kangguo Cheng, Schenectady, NY (US);
Bruce B Doris, Slingerlands, NY (US);
Balasubramanian S Haran, Watervliet, NY (US);
Sanjay Mehta, Niskayuna, NY (US);
Stefan Schmitz, Ballston Spa, NY (US);
Kangguo Cheng, Schenectady, NY (US);
Bruce B Doris, Slingerlands, NY (US);
Balasubramanian S Haran, Watervliet, NY (US);
Sanjay Mehta, Niskayuna, NY (US);
Stefan Schmitz, Ballston Spa, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.