The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2014

Filed:

Sep. 06, 2012
Applicants:

Mohammed Fazil Fayaz, Pleasantville, NY (US);

Jeffery Burton Maxson, New Windsor, NY (US);

Anthony Kendall Stamper, Williston, VT (US);

Daniel Scott Vanslette, Fairfax, VT (US);

Inventors:

Mohammed Fazil Fayaz, Pleasantville, NY (US);

Jeffery Burton Maxson, New Windsor, NY (US);

Anthony Kendall Stamper, Williston, VT (US);

Daniel Scott Vanslette, Fairfax, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 3/30 (2006.01); H01L 23/522 (2006.01); H01L 23/31 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/522 (2013.01); H01L 2224/13022 (2013.01); H01L 24/11 (2013.01); H01L 23/3157 (2013.01); H01L 2924/3511 (2013.01); H01L 2224/131 (2013.01); H01L 2924/01019 (2013.01); H01L 21/76801 (2013.01); H01L 2224/05572 (2013.01); H01L 24/13 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); Y10S 438/925 (2013.01);
Abstract

Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers.


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