The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2014

Filed:

Aug. 03, 2012
Applicants:

William F. Clark, Jr., Essex Junction, VT (US);

Qizhi Liu, Lexington, MA (US);

John J. Pekarik, Underhill, VT (US);

Yun Shi, South Burlington, VT (US);

Yanli Zhang, San Jose, CA (US);

Inventors:

William F. Clark, Jr., Essex Junction, VT (US);

Qizhi Liu, Lexington, MA (US);

John J. Pekarik, Underhill, VT (US);

Yun Shi, South Burlington, VT (US);

Yanli Zhang, San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 21/8249 (2006.01); H01L 21/336 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823418 (2013.01); H01L 29/402 (2013.01);
Abstract

Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region.


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