The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2014

Filed:

Aug. 09, 2010
Applicants:

Yung Fu Chong, Singapore, SG;

Zhijiong Luo, Carmel, NY (US);

Judson Holt, Wappinger Falls, NY (US);

Inventors:

Yung Fu Chong, Singapore, SG;

Zhijiong Luo, Carmel, NY (US);

Judson Holt, Wappinger Falls, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66628 (2013.01); H01L 29/6656 (2013.01); H01L 29/66636 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01);
Abstract

The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.


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