The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2014

Filed:

Nov. 30, 2010
Applicants:

Kazushige Takaishi, Tokyo, JP;

Keiichi Takanashi, Tokyo, JP;

Tetsurou Taniguchi, Tokyo, JP;

Shinichi Ogata, Tokyo, JP;

Shunsuke Mikuriya, Tokyo, JP;

Inventors:

Kazushige Takaishi, Tokyo, JP;

Keiichi Takanashi, Tokyo, JP;

Tetsurou Taniguchi, Tokyo, JP;

Shinichi Ogata, Tokyo, JP;

Shunsuke Mikuriya, Tokyo, JP;

Assignee:

Sumco Corporation, Tokyo, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
B24B 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An object of the present invention is to provide a method of polishing silicon wafers, capable of suppressing generation of undesired sounds from carriers and reducing the thickness variation of the wafers after polished. The method is a wafer polishing method in which wafersare polished by supplying a polishing solution to surfacesof a pair of polishing padspositioned above and below carrierseach having a circular holefor retaining the wafers, the carriersbeing thinner than the wafers; and sliding the polishing padsrelatively to the carriers, thereby simultaneously polishing both surfaces of the wafersretained in the carriers. The method is characterized in that information sourced from the carrierswhen a difference between the thickness of the carriersand the thickness of the wafersreaches a predetermined value is detected to calculate the thickness of the wafers, thereby terminating polishing.


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