The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2014

Filed:

Dec. 11, 2008
Applicants:

Ho-in Ryu, Suwon-si, KR;

Bong-su Kim, Sungnam-si, KR;

Dae-ik Kim, Yongin-si, KR;

Ho-jun Lee, Yongin-si, KR;

Dae-young Jang, Hwasung-si, KR;

Si-hyung Lee, Suwon-Si, KR;

Inventors:

Ho-In Ryu, Suwon-si, KR;

Bong-Su Kim, Sungnam-si, KR;

Dae-Ik Kim, Yongin-si, KR;

Ho-Jun Lee, Yongin-si, KR;

Dae-Young Jang, Hwasung-si, KR;

Si-Hyung Lee, Suwon-Si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4236 (2013.01); H01L 29/66621 (2013.01);
Abstract

A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.


Find Patent Forward Citations

Loading…