The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2014

Filed:

Dec. 14, 2012
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Deepanshu Dutta, Santa Clara, CA (US);

Shinji Sato, Chigasaki, JP;

Masaaki Higashitani, Cupertino, CA (US);

Dengtao Zhao, Santa Clara, CA (US);

Sanghyun Lee, Davis, CA (US);

Assignee:

Sandisk Technologies Inc., Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 29/792 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); G11C 16/10 (2006.01); H01L 29/788 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); H01L 21/28273 (2013.01); H01L 29/66825 (2013.01); H01L 27/11524 (2013.01); G11C 16/0483 (2013.01); H01L 29/788 (2013.01); H01L 29/7887 (2013.01);
Abstract

A non-volatile storage system includes memory cells with floating gates that comprises three layers separated by two dielectric layers (an upper dielectric layer and lower dielectric layer). The dielectric layers may be an oxide layers, nitride layers, combinations of oxide and nitride, or some other suitable dielectric material. The lower dielectric layer is close to the bottom of the floating gate (near interface between floating gate and tunnel dielectric), while the upper dielectric layer is close to top of the floating gate (near interface between floating gate and inter-gate dielectric).


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