The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2014
Filed:
Sep. 28, 2010
DE Yuan Xiao, Shanghai, CN;
Guo Qing Chen, Shanghai, CN;
Roger Lee, Shanghai, CN;
Chin Fu Yen, Shanghai, CN;
Su Xing, Shanghai, CN;
Xiao LU Huang, Shanghai, CN;
Yong Sheng Yang, Shanghai, CN;
De Yuan Xiao, Shanghai, CN;
Guo Qing Chen, Shanghai, CN;
Roger Lee, Shanghai, CN;
Chin Fu Yen, Shanghai, CN;
Su Xing, Shanghai, CN;
Xiao Lu Huang, Shanghai, CN;
Yong Sheng Yang, Shanghai, CN;
Semiconductor Manufacturing International (Shanghai) Corp., Shanghai, CN;
Semiconductor Manufacturing International (Beijing) Corp., Beijing, CN;
Abstract
A system and method for integrated circuits with surrounding gate structures are disclosed. The integrated circuits system includes a transistor having a gate all around cylindrical (GAAC) nanowire channel with an interposed dielectric layer. The cylindrical nanowire channel being in a middle section of a semiconductor wire pattern connects the source and drain region positioned at the two opposite end sections of the same wire pattern. A method is provided for manufacturing the integrate circuits system with a GAAC transistor including forming an SOI layer wire pattern on the buried oxide layer of an SOI wafer; forming a cavity underneath the middle section of the wire pattern and shaping the middle section to cylindrically shaped channel; forming a gate electrode surrounding the cylindrical channel region with an interposed gate dielectric layer, the gate electrode being positioned on the buried oxide layer vertically towards the wire pattern; forming the source/drain regions at the two opposite end sections of the wire pattern on either sides of the gate electrode and channel.