The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 04, 2014
Filed:
May. 14, 2012
Shih-hung Tsai, Tainan, TW;
Ssu-i Fu, Kaohsiung, TW;
Ying-tsung Chen, Kaohsiung, TW;
Chih-wei Chen, Taichung, TW;
Chien-ting Lin, Hsinchu, TW;
Wen-tai Chiang, Tainan, TW;
Shih-Hung Tsai, Tainan, TW;
Ssu-I Fu, Kaohsiung, TW;
Ying-Tsung Chen, Kaohsiung, TW;
Chih-Wei Chen, Taichung, TW;
Chien-Ting Lin, Hsinchu, TW;
Wen-Tai Chiang, Tainan, TW;
United Microelectronics Corp., Hsinchu, TW;
Abstract
A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.