The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2014
Filed:
Jul. 31, 2012
Shih-hung Tsai, Tainan, TW;
Ssu-i Fu, Kaohsiung, TW;
Ying-tsung Chen, Kaohsiung, TW;
Chih-wei Chen, Taichung, TW;
Ying-chih Lin, Tainan, TW;
Chien-ting Lin, Hsinchu, TW;
Hsuan-hsu Chen, Tainan, TW;
Shih-Hung Tsai, Tainan, TW;
Ssu-I Fu, Kaohsiung, TW;
Ying-Tsung Chen, Kaohsiung, TW;
Chih-Wei Chen, Taichung, TW;
Ying-Chih Lin, Tainan, TW;
Chien-Ting Lin, Hsinchu, TW;
Hsuan-Hsu Chen, Tainan, TW;
United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.