The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2014

Filed:

Nov. 13, 2012
Applicant:

Renesas Electronics Corporation, Kawasaki, JP;

Inventors:

Toshiaki Iwamatsu, Kawasaki, JP;

Katsuyuki Horita, Kawasaki, JP;

Hideki Makiyama, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 27/11 (2006.01); H01L 27/02 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 21/84 (2013.01); H01L 27/1207 (2013.01); H01L 29/78648 (2013.01); H01L 27/1116 (2013.01); H01L 27/1108 (2013.01);
Abstract

Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor.


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