The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2014

Filed:

Aug. 03, 2011
Applicants:

Anurag Jindal, Boise, ID (US);

Gowri Damarla, Boise, ID (US);

Roger W. Lindsay, Boise, ID (US);

Eric Blomiley, Boise, ID (US);

Inventors:

Anurag Jindal, Boise, ID (US);

Gowri Damarla, Boise, ID (US);

Roger W. Lindsay, Boise, ID (US);

Eric Blomiley, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 27/115 (2006.01); H01L 21/3213 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 21/32134 (2013.01); H01L 21/02057 (2013.01);
Abstract

Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.


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