The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2014
Filed:
Dec. 31, 2009
Bryan L. Spry, Portland, OR (US);
Theodore Z. Schoenborn, Portland, OR (US);
Philip Abraham, Beaverton, OR (US);
Christopher P. Mozak, Beaverton, OR (US);
David G. Ellis, Beaverton, OR (US);
Jay J. Nejedlo, Wilsonville, OR (US);
Bruce Querbach, Hillsboro, OR (US);
Zvika Greenfield, Kfar Sava, IL;
Rony Ghattas, Hillsboro, OR (US);
Jayasekhar Tholiyil, Hillsboro, OR (US);
Charles D. Lucas, Bonney Lake, WA (US);
Christopher E. Yunker, Beaverton, OR (US);
Bryan L. Spry, Portland, OR (US);
Theodore Z. Schoenborn, Portland, OR (US);
Philip Abraham, Beaverton, OR (US);
Christopher P. Mozak, Beaverton, OR (US);
David G. Ellis, Beaverton, OR (US);
Jay J. Nejedlo, Wilsonville, OR (US);
Bruce Querbach, Hillsboro, OR (US);
Zvika Greenfield, Kfar Sava, IL;
Rony Ghattas, Hillsboro, OR (US);
Jayasekhar Tholiyil, Hillsboro, OR (US);
Charles D. Lucas, Bonney Lake, WA (US);
Christopher E. Yunker, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.