The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2014

Filed:

May. 11, 2011
Applicants:

Ping-hung Tsai, Hsinchu, TW;

Jyun-siang Huang, Hsinchu, TW;

Wen-jer Tsai, Hsinchu, TW;

Inventors:

Ping-Hung Tsai, Hsinchu, TW;

Jyun-Siang Huang, Hsinchu, TW;

Wen-Jer Tsai, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 16/34 (2006.01); G11C 16/32 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); G11C 16/3454 (2013.01); G11C 16/32 (2013.01); G11C 16/0433 (2013.01);
Abstract

A method of programming a memory is provided. The memory has a first cell, having a first S/D region and a second S/D region shared with a second cell. The second cell has a third S/D region opposite to the second S/D region. When programming the first cell, a first voltage is applied to a control gate of the first cell, a second voltage is applied to a control gate of the second cell to slightly turn on a channel of the second cell, a third and a fourth voltage are respectively applied to the first and the third S/D regions, and the second S/D region is floating. A carrier flows from the third S/D region to the first S/D region, and is injected into a charge storage layer of the first cell by source-side injection.


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