The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2014

Filed:

Nov. 30, 2012
Applicant:

Maxim Integrated Products, Inc., San Jose, CA (US);

Inventors:

Viren Khandekar, Flower Mound, TX (US);

Karthik Thambidurai, Plano, TX (US);

Ahmad Ashrafzadeh, Morgan Hill, CA (US);

Amit Kelkar, Flower Mound, TX (US);

Hien D. Nguyen, The Colony, TX (US);

Assignee:

Maxim Integrated Products, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 23/50 (2006.01);
U.S. Cl.
CPC ...
H01L 23/29 (2013.01); H01L 25/0657 (2013.01); H01L 24/17 (2013.01); H01L 2224/05571 (2013.01); H01L 24/03 (2013.01); H01L 2224/03903 (2013.01); H01L 2224/11422 (2013.01); H01L 2225/06513 (2013.01); H01L 2224/02379 (2013.01); H01L 21/56 (2013.01); H01L 24/13 (2013.01); H01L 24/06 (2013.01); H01L 23/3114 (2013.01); H01L 24/14 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/0603 (2013.01); H01L 24/05 (2013.01); H01L 2224/94 (2013.01); H01L 2224/05541 (2013.01); H01L 2224/05008 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/13111 (2013.01); H01L 23/50 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/0348 (2013.01); H01L 2225/06548 (2013.01); H01L 24/11 (2013.01); H01L 24/16 (2013.01); H01L 2224/0391 (2013.01); H01L 21/561 (2013.01);
Abstract

Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.


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