The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2014

Filed:

Jun. 29, 2011
Applicants:

Chao-yang Yeh, Luzhou, TW;

Ze-ming Wu, Tainan, TW;

Meng-lin Chung, Taipei, TW;

Chih-chia Chen, Taipei, TW;

Li-fu Ding, Hsinchu, TW;

Sa-lly Liu, Hsinchu, TW;

Inventors:

Chao-Yang Yeh, Luzhou, TW;

Ze-Ming Wu, Tainan, TW;

Meng-Lin Chung, Taipei, TW;

Chih-Chia Chen, Taipei, TW;

Li-Fu Ding, Hsinchu, TW;

Sa-Lly Liu, Hsinchu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5036 (2013.01);
Abstract

A method comprises analyzing front side conductive patterns and back side conductive patterns on a semiconductor interposer using a machine implemented RC extraction tool, and outputting data representing a plurality of respective RC nodes from the RC extraction tool to a tangible persistent machine readable storage medium. A substrate mesh model of the semiconductor interposer is generated, having a plurality of substrate mesh nodes. Each substrate mesh node is connected to adjacent ones of the plurality of substrate mesh nodes by respective substrate impedance elements. A set of inputs to a timing analysis tool is formed. The plurality of RC nodes are connected to ones of the plurality of substrate mesh nodes of the substrate mesh model. The set of inputs is stored in a tangible machine readable storage medium.


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