The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2014
Filed:
Nov. 01, 2012
Ching-te Chuang, New Taipei, TW;
Nan-chun Lien, Taipei, TW;
Wei-nan Liao, Taichung, TW;
Chi-hsin Chang, Taichung, TW;
Hao-i Yang, Taipei, TW;
Wei Hwang, Hsinchu, TW;
Ming-hsien Tu, Hsinchu, TW;
Ching-Te Chuang, New Taipei, TW;
Nan-Chun Lien, Taipei, TW;
Wei-Nan Liao, Taichung, TW;
Chi-Hsin Chang, Taichung, TW;
Hao-I Yang, Taipei, TW;
Wei Hwang, Hsinchu, TW;
Ming-Hsien Tu, Hsinchu, TW;
Faraday Technology Corp., Science-Based Industrial Park, Hsin-Chu, TW;
National Chiao Tung University, Hsinchu, TW;
Abstract
A static random access memory apparatus and a bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.