The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2014
Filed:
Aug. 24, 2012
Amol Joshi, Sunnyvale, CA (US);
Charlene Chen, San Jose, CA (US);
John Foster, Mountain View, CA (US);
Zhendong Hong, San Jose, CA (US);
Olov Karlsson, San Jose, CA (US);
Bei LI, Fremont, CA (US);
Dipankar Pramanik, Saratoga, CA (US);
Usha Raghuram, Saratoga, CA (US);
Mark Victor Raymond, Schenectady, NY (US);
Jingang Su, Cupertino, CA (US);
Bin Yang, San Carlos, CA (US);
Amol Joshi, Sunnyvale, CA (US);
Charlene Chen, San Jose, CA (US);
John Foster, Mountain View, CA (US);
Zhendong Hong, San Jose, CA (US);
Olov Karlsson, San Jose, CA (US);
Bei Li, Fremont, CA (US);
Dipankar Pramanik, Saratoga, CA (US);
Usha Raghuram, Saratoga, CA (US);
Mark Victor Raymond, Schenectady, NY (US);
Jingang Su, Cupertino, CA (US);
Bin Yang, San Carlos, CA (US);
Intermolecular, Inc., San Jose, CA (US);
GLOBALFOUNDRIES, Inc., Grand Cayman, KY;
Abstract
Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.