The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2014
Filed:
Aug. 05, 2011
Gin-chen Huang, New Taipei, TW;
Yi-an Lin, Taipei, TW;
Ching-hong Jiang, New Taipei, TW;
Neng-kuo Chen, Tainan County, TW;
Sey-ping Sun, Hsinchu, TW;
Clement Hsingjen Wann, Carmel, NY (US);
Gin-Chen Huang, New Taipei, TW;
Yi-An Lin, Taipei, TW;
Ching-Hong Jiang, New Taipei, TW;
Neng-Kuo Chen, Tainan County, TW;
Sey-Ping Sun, Hsinchu, TW;
Clement Hsingjen Wann, Carmel, NY (US);
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method for fabricating a semiconductor device is disclosed. An exemplary method includes a providing substrate. A dielectric layer is formed over the semiconductor substrate and a stop layer is formed over the dielectric layer. The stop layer and the dielectric layer comprise a different material. The method further includes forming a patterned hard mask layer over the stop layer and etching the semiconductor substrate through the patterned hard mask layer to form a plurality of trenches. The method also includes depositing an isolation material on the semiconductor substrate and substantially filling the plurality of trenches. Thereafter, performing a CMP process on the semiconductor substrate, wherein the CMP process stops on the stop layer.