The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2014
Filed:
Sep. 21, 2011
Wim Deweerd, San Jose, CA (US);
Hanhong Chen, Milpitas, CA (US);
Hiroyuki Ode, Higashihiroshima, JP;
Xiangxin Rui, Campbell, CA (US);
Wim Deweerd, San Jose, CA (US);
Hanhong Chen, Milpitas, CA (US);
Hiroyuki Ode, Higashihiroshima, JP;
Xiangxin Rui, Campbell, CA (US);
Intermolecular, Inc., San Jose, CA (US);
Elpida Memory, Inc., Tokyo, JP;
Abstract
A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited first dielectric layer. The first high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous, doped high k second dielectric material is form on the first dielectric layer. The dopant concentration and the thickness of the second dielectric layer are chosen such that the second dielectric layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the second dielectric layer is formed on the second dielectric layer.