The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 2014
Filed:
Jan. 15, 2008
Applicants:
Jae Hak Yee, Shanghai, CN;
Byoung Wook Jang, Yong-in, KR;
Inventors:
Jae Hak Yee, Shanghai, CN;
Byoung Wook Jang, Yong-in, KR;
Assignee:
STATS ChipPAC Ltd., Singapore, SG;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 31/0203 (2014.01); H01L 23/495 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 25/03 (2006.01); H01L 25/065 (2006.01); H01L 25/10 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 31/0203 (2013.01); H01L 21/568 (2013.01); H01L 23/3107 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/49548 (2013.01); H01L 24/45 (2013.01); H01L 24/97 (2013.01); H01L 25/03 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/97 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06562 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01046 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15311 (2013.01); H01L 24/48 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01028 (2013.01); H01L 2225/1029 (2013.01); H01L 2225/1052 (2013.01); H01L 2924/3511 (2013.01); H01L 2924/12041 (2013.01);
Abstract
An integrated circuit package system includes forming an integrated circuit stack having a bottom non-active side and a top non-active side; connecting an internal interconnect between a lead, having a top side and a bottom side, and the integrated circuit stack; and forming an encapsulation, having both a non-elevated portion and an elevated portion, around the integrated circuit stack and the internal interconnect with the top side exposed at the non-elevated portion, and with the bottom side, the bottom non-active side, and the top non-active side exposed.