The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2014

Filed:

Oct. 01, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd, Hsin-Chu, TW;

Inventors:

Chia-Chu Liu, Shin-Chu, TW;

Kuei-Shun Chen, Hsin-Chu, TW;

Meng-Wei Chen, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01B 13/00 (2006.01); H01L 27/02 (2006.01); H01L 21/311 (2006.01); H01L 21/308 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3086 (2013.01); H01L 27/0207 (2013.01); H01L 21/31144 (2013.01);
Abstract

The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of IC features. The method includes identifying, from the IC design layout, simple features as a first layout wherein the first layout does not violate design rules; and complex features as a second layout wherein the second layout violates the design rules. The method further includes generating a third layout and a fourth layout from the second layout wherein the third layout includes the complex features and connecting features to meet the design rules and the fourth layout includes trimming features.


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Liu, Chia-Chu. (2014). Integrated circuit method with triple patterning (U.S. Patent No. 8840796). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8840796

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