Three-dimensional vertically interconnected structure

Abstract

The present invention discloses a three-dimensional vertically interconnected structure and a fabricating method for the same. The structure comprises at least two layers of chips which are stacked in sequence or stacked together face to face, and an adhesive material is used for adhesion between adjacent layers of said chips, each layer of chips contains a substrate layer and a dielectric layer sequentially bottom to top; an front surface of the chip has a first concave with an annular cross section, and the first concave is filled with metal inside to form a first electrical conductive ring connecting to microelectronic devices inside the chip via a redistribution layer; a first through layers of chips hole having the same radius and center as inner ring of the first electrical conductive ring penetrates the stacked chips and has a first micro electrical conductive pole inside that is electrically connected to the first electrical conductive ring. The three-dimensional vertically interconnected structure of the present invention enhances the strength of the electric interconnection and the adhesion between adjacent layers of chips, and in the meantime the disclosed fabricating method simplifies the process difficulty and therefore improves the yield.