The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2014

Filed:

Sep. 13, 2012
Applicants:

Jonathan E. Faltermeier, Delanson, NY (US);

Veeraraghavan S. Basker, Schenectady, NY (US);

Kangguo Cheng, Schenectady, NY (US);

Theodorus Eduardus Standaert, Clifton Park, NY (US);

Inventors:

Jonathan E. Faltermeier, Delanson, NY (US);

Veeraraghavan S. Basker, Schenectady, NY (US);

Kangguo Cheng, Schenectady, NY (US);

Theodorus Eduardus Standaert, Clifton Park, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8242 (2006.01); H01L 21/20 (2006.01); H01L 29/94 (2006.01); H01L 27/108 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10829 (2013.01); H01L 27/10879 (2013.01); H01L 27/10832 (2013.01); H01L 29/945 (2013.01); H01L 29/66181 (2013.01); H01L 27/10867 (2013.01); H01L 27/10861 (2013.01);
Abstract

A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.


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