The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2014

Filed:

Nov. 28, 2012
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Kai Frohberg, Niederau, DE;

Frank Feustel, Dresden, DE;

Thomas Werner, Reichenberg, DE;

Assignee:

GLOBALFOUNDRIE Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/31 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02107 (2013.01); H01L 21/823475 (2013.01); H01L 21/823425 (2013.01); H01L 21/823871 (2013.01); H01L 21/84 (2013.01); H01L 29/7843 (2013.01); H01L 27/1203 (2013.01); H01L 21/823807 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/823821 (2013.01); H01L 27/1211 (2013.01); H01L 21/845 (2013.01); H01L 29/785 (2013.01);
Abstract

In sophisticated semiconductor devices, an efficient stress decoupling may be accomplished between neighboring transistor elements of a densely packed device region by providing a gap or a stress decoupling region between the corresponding transistors. For example, a gap may be formed in the stress-inducing material so as to reduce the mutual interaction of the stress-inducing material on the closely spaced transistor elements. In some illustrative aspects, the stress-inducing material may be provided as an island for each individual transistor element.


Find Patent Forward Citations

Frohberg, Kai. (2014). Restricted stress regions formed in the contact level of a semiconductor device (U.S. Patent No. 8828887). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8828887

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…