The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2014

Filed:

Jun. 06, 2011
Applicants:

Karthik Ramani, Santa Clara, CA (US);

Hiroyuki Ode, Hiroshima, JP;

Sandra Malhotra, San Jose, CA (US);

Inventors:

Karthik Ramani, Santa Clara, CA (US);

Hiroyuki Ode, Hiroshima, JP;

Sandra Malhotra, San Jose, CA (US);

Assignees:

Intermolecular, Inc., San Jose, CA (US);

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01); H01L 49/02 (2006.01); H01L 29/92 (2006.01);
U.S. Cl.
CPC ...
H01L 28/40 (2013.01); H01L 29/92 (2013.01); H01L 28/65 (2013.01); H01L 28/60 (2013.01);
Abstract

A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal. A dielectric layer is formed over the first electrode. The dielectric layer is subjected to a milliseconds anneal process that serves to crystallize the dielectric material and decrease the concentration of oxygen vacancies.


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