The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 12, 2014
Filed:
May. 29, 2009
Yu Cao, Cupertino, CA (US);
Wenjin Shao, Sunnyvale, CA (US);
Ronaldus Johannes Gijsbertus Goossens, Los Altos, CA (US);
Jun YE, Palo Alto, CA (US);
James Patrick Koonmen, Santa Clara, CA (US);
Yu Cao, Cupertino, CA (US);
Wenjin Shao, Sunnyvale, CA (US);
Ronaldus Johannes Gijsbertus Goossens, Los Altos, CA (US);
Jun Ye, Palo Alto, CA (US);
James Patrick Koonmen, Santa Clara, CA (US);
ASML Netherlands B.V., Veldhoven, NL;
Abstract
Systems and methods for process simulation are described. The methods may use a reference model identifying sensitivity of a reference scanner to a set of tunable parameters. Chip fabrication from a chip design may be simulated using the reference model, wherein the chip design is expressed as one or more masks. An iterative retuning and simulation process may be used to optimize critical dimension in the simulated chip and to obtain convergence of the simulated chip with an expected chip. Additionally, a designer may be provided with a set of results from which an updated chip design is created.