The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 2014
Filed:
Feb. 09, 2012
Tze-chiang Chen, Yorktown Heights, NY (US);
Meikei Ieong, Baoshan Township, Hsinchu County, TW;
Rajarao Jammy, Austin, TX (US);
Mukesh V. Khare, White Plains, NY (US);
Chun-yung Sung, Poughkeepsie, NY (US);
Richard Wise, Newburgh, NY (US);
Hongwen Yan, Somers, NY (US);
Ying Zhang, Yorktown Heights, NY (US);
Tze-Chiang Chen, Yorktown Heights, NY (US);
Meikei Ieong, Baoshan Township, Hsinchu County, TW;
Rajarao Jammy, Austin, TX (US);
Mukesh V. Khare, White Plains, NY (US);
Chun-yung Sung, Poughkeepsie, NY (US);
Richard Wise, Newburgh, NY (US);
Hongwen Yan, Somers, NY (US);
Ying Zhang, Yorktown Heights, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.