Interconnection wires of semiconductor devices

Abstract

Disclosed are a method to fabricate interconnection wires of a semiconductor device in a way to utilize benefits of copper interconnection and low k dielectric insulation while avoiding the problem of low k damage due to etching processes, and so fabricated interconnection wires. The method saves fabrication time and cost by reduced number of steps and also resolves metal gap fill issue. The method may comprise providing layers of a substrate, an etch stop layer and a sacrificial layer, forming first spacers, forming first copper interconnecting wires, removing the first spacers; forming polymer-like second spacers by depositing plasma gases in an etching chamber, forming second metal interconnecting wires, removing the second spacers to define channels interwoven with alternating first and second metal interconnecting wires, forming an anti-diffusion barrier around each of the first and second metal interconnecting wires, and filling the channels with a dielectric material for insulation.